1. Field of the Invention
The present invention relate to a method used to fabricate semiconductor devices, and more specifically to a method used to fabricate a dynamic random access memory, (DRAM), device, using a storage node structure, with a roughened top surface.
2. Description of Prior Art
The semiconductor industry is continually striving to improve the performance of semiconductor devices, while still maintaining, or even decreasing the manufacturing cost of these same semiconductor devices. The advent of micro-miniaturization, or the ability to fabricate semiconductor devices, with sub-micron features, has allowed the industry's performance and cost objectives to be successfully addressed. The use of sub-micron features result in decreases in performance degrading capacitances and resistances, thus allowing improved device performance to be realized. In addition the use of micro-miniaturization allows smaller chips, still containing circuit densities comparable to circuit densities obtained with larger semiconductor chips, to be fabricated. This in turn results in an increase in the amount of semiconductor chips obtained from a specific size starting substrate, thus resulting in a reduction of manufacturing cost of a specific chip.
Dynamic random access memory, (DRAM), devices, are being fabricated using a stacked capacitor, (STC), structure, overlying a transfer gate transistor. The shrinking of device features has resulted in a decrease in STC dimensions. Therefore the capacitance of the STC structure, influenced by the dimensions of the storage node electrode, has to be increased via other means. The use of thinner capacitor dielectric layers, or higher dielectric constant materials, used to increase STC capacitance, is limited by process complexity or yield concerns. Therefore the DRAM community has focused on capacitance increases via the creation of storage node electrodes, exhibiting a roughened topology, or a top surface comprised of concave and convex features. The use of a storage node electrode, with a roughened top surface topology, results in an increase in surface area, when compared to counterparts fabricated with a smooth top surface topology, thus resulting in an increase in STC capacitance.
One method of creating a storage node electrode, with a roughened surface, is the formation of an overlying hemispherical grained silicon, (HSG), layer. The ability to create the HSG layer, comprised of silicon bumps, results in surface area increases. Prior art, such as Weimer, et al, in U.S. Pat. No. 5,634,974, describes a method for formation of an HSG silicon layer, to be used as the top layer for a storage node structure. However the method chosen by Weimer, et al, is complex in regards to initially forming silicon seeds, followed by critical annealing procedures. This invention will describe an alternative to HSG silicon, for providing increased surface area for a storage node electrode, resulting in the improved STC capacitance needed for high density DRAM devices. This invention will describe the formation of, and the removal of, a metal silicide layer, from the surface of a storage node electrode, resulting in a roughened, or creviced surface, of polysilicon storage node electrode, resulting in increased surface area, without using HSG silicon layers.